Modern integrated circuits are getting more and more complex. In order to evaluate the functionality of integrated circuits various testing techniques were developed.
Testers inject test vectors that include timing signals and data signals to a tested device (also known as device under test or DUT), receive a test response from the tested device and evaluate the functionality of the tested device by analyzing the test response. The test vector is usually very long and can be represented by a two dimensional matrix. The rows of the matrix represent different points in time (different samples) while the columns of the matrix represent input signals.
The test vectors are usually very long, as modern integrated circuit (and especially multiple core integrated circuits) include many pins and can receive a large number of signals over relatively long periods.
Test vectors are usually generated by a pattern generator in response to the expected functionality of the tested device, in response to a simulation of the tested device, and the like. Testing communication controllers usually involves generating a test vector by simulating another communication controller that exchanges many signals with the tested communication controller.
The test vectors are very long and usually cannot be updated on-the fly, as they represent the simulated response of a highly complex simulation. In many cases a change in a test vector is a highly complex and long process during which there is a need to update the model that forms the basis of the pattern generation. In addition, a requested test vector change should be checked in order to prevent damages to the tested circuit or a provision of prohibited (or invalid) test signal combinations.
This robust approach does not necessarily meet the dynamic environment of modern integrated circuit vendors and clients. In many cases the demands from a device can change rapidly and there is a need to provide an efficient method and device for testing a device.